Logic devices such as FPGAs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, placement, and routing.
During synthesis, a designer inputs a description of the system into the EDA tool. The EDA tool may perform synthesis procedures such as extraction, logic minimization, and technology mapping on the description of the system and produce a cell netlist. The EDA tool may be configured with various settings for the extraction, logic minimization, and technology mapping procedures. For example, for logic minimization, a designer may select a setting that directs the EDA tool to choose one of many state machine encoding methods. For technology mapping, a designer may select a setting that directs the EDA tool to honor or to ignore classes of user buffers. These selections may affect the area and speed of portions of the system. An EDA tool may have thousands of such settings that may be programmed by a designer.
Typically, certain portions of a system may work better with certain EDA tool settings than with others. When programmed, settings are applied to the entire design and the benefits of a selected setting is often not known until after synthesis is performed on the system.